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Giáo trình Kỹ thuật Vi xử lý - Chương 4

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Nội dung text: Giáo trình Kỹ thuật Vi xử lý - Chương 4

  1. KK thuthu tt ViVi xx lýlý oaoa
  2. ưư oo oo aa oo aa uu aa oo
  3. MMụụcc tiêutiêu vv àà bibi ệệnn phph áápp thithi ếếtt kk ếế  uu aooaoo yaya uu uyuy oo uyuy  aa oo oo oo aa
  4. 4.14.1 PhânPhân lolo ạạii bb ộộ nhnh ớớ bbáánn dd ẫẫnn B nh bán d n (Semiconductor memory ) SAM RAM (Sequential Access Memory) (Random Access Memory) ROM (Read Only Mem ory ) RWM (Read Write memory) PROM EPROM SRAM DRAM EEPROM Flash ROM
  5. 4.24.2 CCáácc chipchip EPROMEPROM A0 D0 A1 D1 A2 D2 A3 D3 u A4 D4 a A5 D5 A6 D6 A7 Dm-1 A8 A p-1 u OE PGM CE Vpp u
  6. DungDung ngng cc aa 11 chipchip nhnh  ưư eưeư ưuưu ưư uu  uu ưư aa ưư ưư uu uu ưư aa ưuưu ưư yeye uu  uu aa  oo aa aa
  7. HoHo tt ngng ghighi dd lili uu vv ààoo EPROMEPROM  uu oo ưư oo  ưư uyuy  ưư ưư oo  uu uu ưư oo uu ưaưa oo aa uu ưư uu ưaưa oo
  8. HoHo tt ngng cc dd lili uu tt mmtt chipchip EPROMEPROM uu oo aa oo   u a a o a   u u u u
  9. HH EPROMEPROM thôngthông dd ngng 27x27x uu aa uu ưư
  10. EPROM 2716 2732 1 24 A7 Vcc 2 23 A6 A8 3 22  A5 A9 4 21 aa A4 Vpp A11 5 20 __ __ A3 OE OE / Vpp 6 19 A2 A10 __ 7 18 A1 CE 8 17 A0 D7 9 16 D0 D6 10 15 D1 D5 11 14 D2 D4 12 13 GND D3
  11. EPROMEPROM 27642764 a u u
  12. EPROMEPROM 27642764
  13. LLpp trtr ììnhnh chocho 27642764  ưư oo • o o  oo aa  • • u  uưauưa oo uu  aa ưaưa oo aa
  14. 4.34.3 CCáácc chipchip SRAMSRAM A0 D0 A1 D1 A2 D2 A3 D3 A4 D4 u a A5 D5 A6 D6 A7 Dm-1 A8 A p-1 u OE CS u WE
  15. cc dd lili uu tt mmtt chipchip SRAMSRAM uu oo aa oo   uu aa oo  uu uu uu uu
  16. GhiGhi dd lili uu vv ààoo mm tt chipchip SRAMSRAM uu oo oo aa oo   uu aa oo  uu oo uu  uu uu uu ưư oo
  17. 4.44.4 BusBus hh thth ngng cc aa 80888088  uu aa ưư aa ưư uu  uu uu ưư uu ưư uu  uu uu ưư uu oooo uyuy ưư ưư ưư uu aa uu uu  uu aa uaua
  18. 80x8680x86 MicroprocessorsMicroprocessors Product 8008 808 808 808 808 8028 80386 80486 Pent. Pent. 0 5 6 8 6 Pro eaoue eooy oae ueo ueo ao ueo uo yaeoy uaeoy oe oe oe oe oe eaaau eaaau eu aaye
  19. 8088/80868088/8086 MicroprocessorMicroprocessor   aauaau uu uu oo uu uu oo aa uu uu oo aa eaaeeaae
  20. 8088/80868088/8086 MicroprocessorMicroprocessor  uu aa aa  u o o  ua o
  21. SSơơ chânchân cc aa 80888088
  22. SSơơ chânchân 8088/80868088/8086 (Min(Min Mode)Mode)
  23. Minimum/MaximumMinimum/Maximum ModeMode  ưư  uoeuoe u u u u u ư  auoeauoe u u ư oa o o
  24. SSơơ chânchân cc aa 80888088 MN / MX AD0 AD1 READY AD2 CLK AD3 RESET AD4 AD5 TEST AD6 AD7 HLDA A8 HOLD A9 NMI A10 A11 A12 A13 A14 8088 A15 A16 / S3 A17 / S4 A18 / S5 A19 / S6 SSO DEN DT / R IO / M RD WR ALE INTR INTA
  25. Tín hi u các chân c a 8088 MN / MX AD0 AD1 READY AD2 CLK AD3 RESET AD4 Các chân a ch /D li u AD5 TEST AD6 AD7 HLDA A8 HOLD A9 NMI A10 A11 A12 Các chân a ch A13 A14 8088 A15 A16 / S3 A17 / S4 Các chân a ch /Tr ng thái A18 / S5 A19 / S6 SSO DEN DT / R IO / M RD WR ALE Cho phép ch t a ch INTR INTA
  26. CCáácc chânchân aa chch /D/D lili uu   uu ueue uu yy yy uu aa uu uu uu oo uu uu ee aaeaae  
  27. CCáácc chânchân aa chch vvàà CCáácc chânchân aa chch //TrTr ngng thth ááii  aa  uu yuyu uu aa  aa  
  28. Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read (with 74245) T1 T2 T3 T4 CLOCK __ DT/R ALE D7 - D0 D7 - D0 (from memory) from memory to 74LS245 D7 - D0 from garbage AD7 - AD0 A7 - A0 74LS245 A15 - A8 A15 - A8 A19/S6 - A16/S3 A19 - A16 S6 - S3 A19 - A0 A19 - A0 from 74LS373 from 74LS373 to memory __ IO/M if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW ___ RD ___ DEN
  29. MôMô tt chânchân   uaeuae  yeye yeye aoao aa
  30. MôMô tt chânchân   oaaeoaae eueu  uu oo eưeư
  31. MôMô tt chânchân   eueueeueue  uu oo ee ưư  uu 
  32. MôMô tt chânchân   oo  uu oo 
  33. MôMô tt chânchân   o uy  au ee o
  34. MôMô tt chânchân   aaeaae
  35. MôMô tt chânchân   
  36. MôMô tt chânchân   uoeuoe  auoeauoe
  37. MôMô tt chânchân –– MaxMax   ueueauueueau  aa ooeao yeo ooeoueue eyeueue ueueye oueue
  38. MôMô tt chânchân –– MaxMax   aua eu aoee eao eo oe a oeae eaeoy e eoy oe ae
  39. MôMô tt chânchân –– MaxMax   ooeooooeoo yeuyeu  aeoyuaeoyu eoaeoa aeyuoaeyuo  eaueau aoeeaoee oaoa oooeueoooeue
  40. MôMô tt chânchân –– MaxMax   eueaeuea  eoaeoa  aooooaaooooa uu  oayoay eaeyeaey aeae  oeeoee oeoe
  41. MôMô tt chânchân –– MinMin   euaoeeeuaoee 
  42. MôMô tt chânchân –– MinMin   eaea aeae  uu aa uu aa uu aa
  43. MôMô tt chânchân   aa uu  uu yy aa uu
  44. 74LS373 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 74LS373 Q5 D6 Q6 D7 Q7 OE LE
  45. 74LS373
  46. DDùùngng 74LS37374LS373 ttááchch vv àà chch tt aa chch
  47. MôMô tt chânchân –– MinMin   aaaeaaae  uu aa
  48. MôMô tt chânchân –– MinMin   uu ưư aa uu uu  uu uu aa  uu uu oo
  49. MôMô tt chânchân –– MinMin   uyuy ayay uyuy uyuy
  50. MôMô tt chânchân –– MinMin   uu uu uưuư oo oo   uu uaua
  51. MôMô tt chânchân –– MinMin   ooeeooee  yuyu uu oo u ư u
  52. MôMô tt chânchân –– MinMin   uu yuyu uu uu  uu uu
  53. MôMô tt chânchân –– MinMin    auau uu
  54. CCáácc tt íínn hihi uu iiuu khikhi nn  oo oo aa uu uu uu uu uu  a a ee ae
  55. TToo rara cc áácc ttíínn hiêhiê uu khikhi nn (Min(Min Mode)Mode)
  56. TToo rara cc áácc tt íínn hiêhiê uu khikhi nn (Min(Min Mode)Mode)
  57. 80888088 BusBus –– MinMin ModeMode
  58. 74LS24574LS245 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 74LS245 B5 A6 B6 A7 B7 E DIR
  59. Bus h th ng c a h 8088 Mode Minimum A7 - A0 B7 - B0 D7 - D0 DEN E Bus d li u DT / R DIR 74LS245 Bus a ch AD7 - AD0 D7 - D0 Q7 - Q0 A7 - A0 A15 - A8 GND OE A19 - A16 LE 74LS373 A15 - A8 D7 - D0 Q7 - Q0 GND OE MEMORY 8088 LE 74LS373 A19/S6 - A16/ D7 - D4 Q7 - Q4 S3 D3 - D0 Q3 - Q0 GND OE ALE LE 74LS373 RD RD MEMR IO / M WR WR MEMW
  60. Minimum Mode 8088 D7 - D0 D7 - D0 A19 - A0 A19 - A0 MEMORY 8088 Minimum B nh c ch n khi nào? Mode MEMR RD MEMW WR
  61. Minimum Mode 8088 220 ô nh ớ (1MB) D7 - D0 D7 - D0 A19 - A0 A19 - A0 MEMORY 8088 Minimum Mode MEMR RD MEMW WR CS
  62. KhôngKhông giangian aa chch bb nhnh 1M1M A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 98769876 54325432 1010 0000 (HEX)(HEX) 0000000000 00000000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111 Ví d: Mt a ch bt k 34FD0h 0011 0100 11111 1101 0000
  63. B nh y 1MB AX 3F1C FFFFF 36 BX 0023 FFFFE 25 CX 0000 FFFFD 19 DX FCA1 : : A19 A19 : : : : CS XXXX 20023 13 A0 A0 SS XXXX 20022 7D DS 2000 20021 12 ES XXXX 20020 29 : : D7 D7 BP XXXX : : : : SP XXXX 10008 8A D0 D0 10007 F4 SI XXXX 10006 07 DI XXXX 10005 88 10004 42 MEMR RD IP XXXX 10003 39 10002 27 10001 98 10000 45 : : MEMW WR : : 00001 95 CS 00000 23
  64. NNuu chch ccnn bb nhnh ccóó dungdung ngng nhnh ơơ 1MB1MB thth ìì gigi ii quyquy tt nhnh thth nnààoo??  uu oo  uu uu uu aa oo oo auau 
  65. 512K512K uu tiêntiên cc aa khôngkhông giangian aa chch bb nhnh ((CCáácc aa chch ccóó bitbit caocao nhnh tt A19A19 == 0)0) A18A18 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 99876876 54325432 1010 0000 (HEX)(HEX) 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 00111111 11111111 11111111 11111111 11111111
  66. 512K512K titi pp theotheo cc aa khôngkhông giangian aa chch bb nhnh ((CCáácc aa chch ccóó bitbit caocao nhnh tt A19A19 == 1)1) A18A18 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 99876876 54325432 1010 0000 (HEX)(HEX) 8000080000 11000000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111
  67. B nh 512KB AX 3F1C BX 0023 Làm gì vi A19? CX 0000 A19 DX FCA1 A18 A18 7FFFF 36 : : 7FFFE 25 CS XXXX A0 A0 7FFFD 19 SS XXXX : : DS 2000 D7 D7 : : ES XXXX : : 20023 13 D0 D0 20022 7D BP XXXX 20021 12 SP XXXX MEMR RD 20020 29 : : SI XXXX MEMW WR : : DI XXXX 00001 95 CS 00000 23 IP XXXX
  68. iu gì xy ra nu 8088 c ô nh A0023h? AX 3F1C BX 0023 CX 0000 A19 DX FCA1 A18 A18 7FFFF 36 : : 7FFFE 25 CS XXXX A0 A0 7FFFD 19 SS XXXX : : DS A000 D7 D7 : : ES XXXX : : 20023 13 D0 D0 20022 7D BP XXXX 20021 12 SP XXXX MEMR RD 20020 29 : : SI XXXX MEMW WR : : DI XXXX 00001 95 CS 00000 23 IP XXXX MOV AH, [BX]
  69. iu g ì xy ra n u 8088 c ô nh A0023h? A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 99876876 54325432 1010 0000 (HEX)(HEX) A0023A0023 11010010 00000000 00000000 00100010 00110011 A19 không được nối đến bộ nh ớ nên nếu 8088 phát logic “1” trên A19 thì bộ nh ớ cũng không nh ận bi ết được.
  70. iu g ì xy ra n u 8088 c ô nh 20023h? A18A18 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 99876876 54325432 1010 0000 (HEX)(HEX) 2002320023 00010010 00000000 00000000 00100010 00110011 Với b ộ nh ớ tình hình không có gì khác!
  71. Nu B nh gm 2 kh i 512KB nh th này? AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX 7FFFF 12 DI XXXX A18 7FFFE 98 : 7FFFD 2C IP XXXX A0 : : 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  72. CCóó vvnn !!!!!!  uu uu aa uu uu  ưư uyuy uu uu uu oo oo ưư ưư
  73. B nh gm hai kh i nh 512KB AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX 7FFFF 12 DI XXXX A18 7FFFE 98 : 7FFFD 2C IP XXXX A0 : : 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  74. KhôngKhông giangian aa chch bb nhnh 1M1M A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA đđếếnn 11111111 11111111 11981198 76547654 32103210 A0 A0 98769876 54325432 1010 0000 (HEX)(HEX) 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 01110111 11111111 11111111 11111111 11111111 8000080000 10001000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111
  75. Interfacing two 512KB Memory to the 8088 Microprocessor AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX When the µP outputs CS 00000 23 SP XXXX an address between SI XXXX 8000000000 to FFFFF7FFFF , 7FFFF 12 DI XXXX A18 7FFFE 98 this memory is : 7FFFD 2C IP XXXX A0 : : selected 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  76. Interfacing two 512KB Memory to the 8088 Microprocessor AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX 7FFFF 12 DI XXXX A18 7FFFE 98 : 7FFFD 2C IP XXXX A0 : : 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  77. Interfacing two 512KB Memory to the 8088 Microprocessor AX 3F1C A19 A19 7FFFF 36 BX 0023 A18 A18 A18 7FFFE 25 CX 0000 : : : 7FFFD 19 DX FCA1 A0 A0 A0 : : 20023 13 D7 D7 D7 CS XXXX 20022 7D : : : SS XXXX 20021 12 D0 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD RD : : MEMW WR WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX 7FFFF 12 DI XXXX A18 7FFFE 98 : 7FFFD 2C IP XXXX A0 : : 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  78. What if we remove the lower memory? AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX 7FFFF 12 DI XXXX A18 7FFFE 98 : 7FFFD 2C IP XXXX A0 : : 20023 33 D7 20022 45 : 20021 92 D0 20020 A3 RD : : WR 00001 D4 CS 00000 97
  79. What if we remove the lower memory? AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX When the µP outputs CS 00000 23 SP XXXX an address between SI XXXX 8000000000 to FFFFF7FFFF , no DI XXXX thismemory memory chip is is IP XXXX selected !
  80. FullFull andand PartialPartial DecodingDecoding  ueoueo eaoeeaoe ueuueu aeeaee aeoeeeeoyeeoaeoeeeeoyeeo eoeeoeoeeo  aaeoaaeo eoeoeeoeoe ueuueu aeeaee aeoeeeeoyeeoaeoeeeeoyeeo eoeeoeoeeo yeoeoeuoyeoeoeuo oo oeaeeoeaee
  81. Full Decoding AX 3F1C A19 7FFFF 36 BX 0023 A18 A18 7FFFE 25 CX 0000 : : 7FFFD 19 DX FCA1 A0 A0 : : 20023 13 D7 D7 CS XXXX 20022 7D : : SS XXXX 20021 12 D0 D0 DS 2000 20020 29 ES XXXX MEMR RD : : MEMW WR 00001 95 BP XXXX CS 00000 23 SP XXXX SI XXXX DI XXXX IP XXXX
  82. FullFull DecodingDecoding A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000 8000080000 10001000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111 A19 should be a logic “1” for the memory chip to be enabled
  83. FullFull DecodingDecoding A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 01110111 11111111 11111111 11111111 11111111 Therefore if the microprocessor outputs an address between 00000 to 7FFFF, whose A19 is a logic “0”, the memory chip will not be selected
  84. Partial Decoding AX 3F1C BX 0023 CX 0000 A19 DX FCA1 A18 A18 7FFFF 36 : : 7FFFE 25 CS XXXX A0 A0 7FFFD 19 SS XXXX : : DS 2000 D7 D7 : : ES XXXX : : 20023 13 D0 D0 20022 7D BP XXXX 20021 12 SP XXXX MEMR RD 20020 29 : : SI XXXX MEMW WR : : DI XXXX 00001 95 CS 00000 23 IP XXXX
  85. PartialPartial DecodingDecoding A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 01110111 11111111 11111111 11111111 11111111 8000080000 10001000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111 The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not
  86. PartialPartial DecodingDecoding A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 01110111 11111111 11111111 11111111 11111111 8000080000 10001000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111 ACTUAL ADDRESS
  87. PartialPartial DecodingDecoding A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000 0000000000 00000000 00000000 00000000 00000000 00000000 7FFFF7FFFF 01110111 11111111 11111111 11111111 11111111 8000080000 10001000 00000000 00000000 00000000 00000000 FFFFFFFFFF 11111111 11111111 11111111 11111111 11111111 ACTUAL ADDRESS
  88. Interfacing two 512K Memory Chips to the 8088 Microprocessor A19 A18 A18 : : A0 A0 D7 D7 512KB : : #2 D0 D0 MEMR RD MEMW WR 8088 CS Minimum Mode A18 : A0 D7 512KB : #1 D0 RD WR CS
  89. Interfacing one 512K Memory Chips to the 8088 Microprocessor A19 A18 A18 : : A0 A0 D7 D7 : : 512KB D0 D0 MEMR RD MEMW WR 8088 CS Minimum Mode
  90. Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2) A19 A18 A18 : : A0 A0 D7 D7 : : 512KB D0 D0 MEMR RD MEMW WR 8088 CS Minimum Mode
  91. Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3) A19 A18 A18 : : A0 A0 D7 D7 : : 512KB D0 D0 MEMR RD MEMW WR 8088 CS Minimum Mode
  92. Interfacing four 256K A17 : Memory Chips to A0 Memory Chips to D7 256KB : the 8088 Microprocessor D0 #4 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : D0 D0 #3 MEMR RD MEMW WR 8088 CS Minimum Mode A17 : A0 D7 256KB : D0 #2 RD WR CS A17 : A0 D7 256KB : D0 #1 RD WR CS
  93. Interfacing four 256K A17 : A0 Memory Chips to D7 256KB : the 8088 Microprocessor D0 #4 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : D0 D0 #3 MEMR RD MEMW WR 8088 CS Minimum Mode A17 : A0 D7 256KB : D0 #2 RD WR CS A17 : A0 D7 256KB : D0 #1 RD WR CS
  94. MemoryMemory chip#__chip#__ isis mappedmapped to:to: A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000
  95. Interfacing four 256K A17 : A0 Memory Chips to D7 256KB : the 8088 Microprocessor D0 #4 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : D0 D0 #3 MEMR RD MEMW WR 8088 CS Minimum Mode A17 : A0 D7 256KB : D0 #2 RD WR CS A17 : A0 D7 256KB : D0 #1 RD WR CS
  96. Interfacing four 256K A17 : A0 Memory Chips to D7 Memory Chips to 256KB : the 8088 Microprocessor D0 #4 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : D0 D0 #3 MEMR RD MEMW WR 8088 CS Minimum Mode A17 : A0 D7 256KB : D0 #2 RD WR CS A17 : A0 D7 256KB : D0 #1 RD WR CS
  97. Interfacing four 256K A17 : A0 Memory Chips to D7 Memory Chips to 256KB : the 8088 Microprocessor D0 #4 RD WR A19 I1 O3 CS A18 I0 A17 A17 : : A0 A0 D7 D7 256KB : : D0 D0 #3 MEMR RD MEMW WR 8088 O2 CS Minimum Mode A17 : A0 D7 256KB : D0 #2 RD WR O1 CS A17 : A0 D7 256KB : D0 #1 RD WR O0 CS
  98. A12 : Interfacing several A0 A19 D7 8KB A18 : 8K Memory Chips A17 D0 #? A16 RD µ A15 WR to the 8088 P A14 CS A13 A12 : A0 D7 : : D0 MEMR 8088 MEMW : Minimum Mode A12 : A0 D7 8KB : D0 #2 RD WR CS A12 : A0 D7 8KB : D0 #1 RD WR CS
  99. A12 : Interfacing 128 A0 A19 D7 8KB A18 : 8K Memory Chips A17 D0 #128 A16 RD µ A15 WR to the 8088 P A14 CS A13 A12 : A0 D7 : : D0 MEMR 8088 MEMW : Minimum Mode A12 : A0 D7 8KB : D0 #2 RD WR CS A12 : A0 D7 8KB : D0 #1 RD WR CS
  100. A12 : Interfacing 128 A0 A19 D7 8KB A18 : 8K Memory Chips A17 D0 #128 A16 RD to the 8088 µP A15 WR to the 8088 P A14 CS A13 A12 : A0 D7 : : D0 MEMR 8088 MEMW : Minimum Mode A12 : A0 D7 8KB : D0 #2 RD WR CS A12 : A0 D7 8KB : D0 #1 RD WR CS
  101. MemoryMemory chip#__chip#__ isis mappedmapped to:to: A19A19 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA toto A0A0 11111111 11111111 11981198 76547654 32103210 (HEX)(HEX) 98769876 54325432 1010 0000
  102. A12 : Interfacing 128 A0 A19 D7 8KB A18 : 8K Memory Chips A17 D0 #128 A16 RD to the 8088 µP A15 WR to the 8088 P A14 CS A13 A12 : A0 D7 : : D0 MEMR 8088 MEMW : Minimum Mode A12 : A0 D7 8KB : D0 #2 RD WR CS A12 : A0 D7 8KB : D0 #1 RD WR CS