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Bài giảng Các hệ thống Tin học công nghiệp - Chương 5: Programmable Controllers

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  1. Ch. 5 Programmable Controllers  PLC/PC Overview  Siemens SIMATIC S7-x00 seri PLCs  STEP 7 – 300/400 Programming Language  WinCC Ch4 ProgControllers 1 5.1. Khái niệm PLCs  Lịch sử:  1960 – 1970s: Hard wire  1980 – 1990: Programmable Logic Controller  1990 – nay: Programmable Controller, Process Controller  Các hãng sản xuất:  USA: Allen Bradley, GE-Fanuc  EC: Siemens, ABB, Schneider  As-Au: Omron, Hitachi, Misubishi Ch4 ProgControllers 2 1
  2.  Cấu trúc: chia thành các modules:  CPU, Power supply Module có cổng nối bộ lập trình (PG) [Expansion Memory Module (Flash, SRAM, DRAM, BBRAM)] Digital Input Module (mức áp dc/ac, cách ly quang ) Digital Output Module (relay, transistor, triac , Relay/Opto Isolated)  Analog Input Module (u, i, cách ly ) Ch4 ProgControllers 3 Analog Output Module (u, i)  Timer/ Counter Module (kHz, đếm xung, đo tốc độ, chiều dài)  Communication Module: (RS232/485; Ethernet IEEE 802.x)  2/3 D Positioner Module (định vị 2/ 3 chiều)  Interface Module - dùng để mở rộng thêm các Module khác  Function Modules: các chức năng điều khiển PID, Servo/ Step Motors, Ch4 ProgControllers 4 2
  3.  Hoạt động của PLC:  Hoạt động theo chu kỳ các vòng quét: . Đọc các thông tin từ các lối vào: DI, AI, Counter, Communication . Xử lý, tính toán, Update data base, update các cờ trạng thái . Gửi ra các port: DO, AO, Positioner, Communication  Ngôn ngữ lập trình: . Ladder . Statement List . Flow control Ch4 ProgControllers 5 5.2. Siemens SIMATIC S7-x00 PLC: 5.2.1. S7-200: Hình 402. PLC S7-200 Ch4 ProgControllers 6 3
  4.  Micro type, high-speed, compact, low-cost solution for automation tasks within the low-end performance range.  Có nhiều loại CPU: 212 (214 )  RAM for Program & data: . 212 CPU: 1Kbyte – 512 statement, 2048 word data . 214 CPU: 4Kbyte – 2048 statement, 2048 word data  Execution time of 1024Statements: 1,3ms (212CPU) và 0.8ms (214 CPU)  Bit memory: 128 (256)  Counters, Timer: 46 (128)  DI/DO max/onboard: 30/14 (64/24)  AI/AO max: 8 (16)  Communication: PPI Ch4 Real ProgControllers time clock: CPU 214. 7 5.2.2. S7-300 Hình 403a – PLC S7-300 Ch4 ProgControllers 8 4
  5.  Mini PLC system, the custom solution for extremely fast processes/ automation tasks requiring additional data processing capabilities  Spec.:  High computing performance,  Complete instruction set,  Multi Point Interface – MPI  5 CPUs for a wide variety of requirement  Expandability: up to 3 Expansion Racks (ERs) Ch4 ProgControllers 9 Ch4 ProgControllers 10 5
  6. 5.2.3. S7-400: Hình 404a. S7-400 Ch4 ProgControllers 11  Power PLC for automation tasks within mid & upper range:  High Speed, 1K statement – 200 us  Rugged: full enclosed, for industrial environment  Module can be hot pluggible  Communications power house: . Connection to SINEC L2 or SINEC H1 or Point-to- Point . Fast data exchange to the distributed I/Os Ch4 ProgControllers 12 6
  7. Ch4 ProgControllers 13 5.2.4. Programming Devices Hình 405a. Ch4 ProgControllers 14 7
  8. Hình 405b. Ch4 ProgControllers 15 5.2.5. Distributed IOs Ch4 ProgControllersFig. 406. Distributed IO Modules 16 8
  9.  In conventionally automated Plants, IO are plugged directly into PLC. Frequently this leads to extensive wiring with  High cabling cost  Reduced flexibility in the case of modifications and expansions  A distributed configuration means:  The PLCs, IO Modules and Field Devices are connected over a single cable known as a field bus,  The IO Modules can be installed in the immediate vicinity of sensors and actuators  The process signals can be converted and processed locally Ch4 ProgControllers 17 Fig. 406a. SINEC L2-DP with Distributed IO Modules Ch4 ProgControllers 18 9
  10.  The following can be connected to the ProFiBus-DP:  Active Stations: . S/M7 300 – 400 automation systems as well as from other manufacturers . Programming devices and AT compatible PCs . COROS Operator Panels  Passive Stations: . ET200M/L/B/C/U distributed IO Stations, S5 Seri PLCs, DP/AS-I link transceiver . MMI . Additional field Devices as well as third party devices with slave interface Modules Ch4 ProgControllers 19 5.3. SIMATIC SOFTWARE  STEP 7 Mini programming software  STEP 7 Micro/DOS/Win programming software Ch4 ProgControllers 20 10
  11. 5.3.1. Introdution Application: SIMATIC software are array of tools based on standard for PLCs S7  It provides all software functions required for: . Configuring . Programming . Testing . Starting up and . Servicing PLCs Ch4 ProgControllers 21 Design:  Feature: .Comprehensive: –Shared data management; All data of a project are filled in a single central database. –Comprehensive series of tools; for every phase of an automation project there are user- friendly functions: configuration, parameterization of the hardware, creation and documentation of programs, as well as testing, startup and servicing. –Openness: Imp/Exp interface ensure connection with the PC world Ch4 ProgControllers 22 11
  12. .User-friendly: –Individual programming languages, Help and doc. Functions –Extensive set of command and detailed information functions (Err that may occur and their causes ) . Standard: based on Windows OS, satisfy the standard DIN EN 6.1131-3 Ch4 ProgControllers 23 Package: .STEP7 Micro/DOS/WIN: for programming S7-200 .STEP7 Mini: for programming stand-alone S7-300 .STEP7: the universal software for S7-300, -400 .High level programming languages S7- SCL: similar to PASCAL Ch4 ProgControllers 24 12
  13. Technology-Oriented Software Package (w/o knowledge of PLC, computer or programming): S7 Graph: describing event driven processes w sequential Operation. S7 HiGraph: describing event driven processes w non-sequential Operation. Software for special applications: COROS for parameterization of the MMI SIMATIC S7 standard control system Fuzzy control . Ch4 ProgControllers 25 Ch4 ProgControllersFig 407a. STEP7 software package 26 13
  14. Fig 407c. PLC S7 seri software tools Ch4 ProgControllers 27 5.3.2. Micro/DOS/Win for s7-200 Configuring Programming Debugging Testing Ch4 ProgControllers 28 14
  15. 5.3.3. S7-300/400  Configuring  Instruction Set Ch4 ProgControllers 29 5.3.3.1. The modules of S7-300  CPU Modules:  CPU, Mem/OS, Timer, Comm 485, onboard I/O ports (Option)  CPU Module: CPU 312, 314, 315, CPU31x IMF (Integrated Function Module - Onboard I/O & OS)  2 Comm ports CPU - CPU 31x - DP (Ditributed Port): the second for networking. Ch4 ProgControllers 30 15
  16. Expanded Modules: PS - Power Supply: 2, 5, 10 Amp SM - Signal Module: In/Out signal modules: . DI: Digital Input, 8, 16, 32 . DO: Digital Output, 8, 16, 32 . DI/DO 8/8 or 16/16 . AI: 12 bit ADC, 2/4/8 channel . AO: 8/12 bit DAC, 2/4 channel IM: Interface Modules: For expanding more rack. Each rack for 8 modules max (Not including CPU & PS). 1 CPU S7-300 can connect to 4 racks max via IMs. Ch4 ProgControllers 31 FM: Function modules: PID controller, Step motor, servo modules. CP: Communication Modules: to communicate between PLCs and Computers Ch4 ProgControllers 32 16
  17. 5.3.3.2. DATA & MEMORY MAPPING: Data types:  Elementary data types: Ch4 ProgControllers 33 . Bool . Byte: 8 bit or ASCII character: L B#16#14 // load byte 14h into Accu1 . word: L W#16#32A . Int: -32768 +32767: . DInt: 4 byte L DW#16#234F . Real: Floating Point 4 byte . S5T (S5TIME): interval (hh/mm/ss/ms) L S5T#2h_1m_7s_13ms. . TOD - Time of day: hh/mm/ss L TOD#12:34:40. . DATE: L DATE#2004-12-31. . CHAR: max 4 char L 'HE_6' Ch4 ProgControllers 34 17
  18. Complex data types Ch4 ProgControllers 35  Parameter data types Ch4 ProgControllers 36 18
  19.  Memory: 3 parts Ch4 ProgControllers 37  Application Program memory Part - 3 sections: . OB: Organization Block . FC: Function - Sub module with dummy parameters of main program . FB: Function Block: Sub module with data exchange to/from other modules. The data must be DB (data block)  Data Area of OS and Application - 7 sub areas: . I (Process Image Input): data input buffer for DI ports. CPU just read this buffer, not ports . Q (Process Image Output): data output buffer for DO ports. CPU just writes this buffer, not ports . M: Status/Conditional: bit (M), byte (MB), word (MW), double word (MD) . T: Time buffer: preset/current time value and logic output. . C: Counter: preset/current counter value and logic output. . PI: I/O External Input Address for analog inputs: PIB, PIW, PID . PQ: I/O External Output Address for analog outputs: PQB, PQW, PQD  Data Blocks - 2 blocks: . DB: data block, accessible by: DBX (bit), DBB, DBW, DBD . L (Local data blocks) local data memory of OB, FC, FB. Accessible: L (bit), LB, LW, LD. Ch4 ProgControllers 38 19
  20. 5.3.3.3. SCAN LOOP: 4 phases Scan time not fix - tùy nhiều hay ít lệnh Interrupt Service block: OB40, OB80 được thực hiện tại bất kỳ thời điểm nào - không cần trật tự. Ch4 ProgControllers 39 5.3.3.4. PROGRAM STRUCTURES: Linear Programming Structured Programming: OB (Organization Blocks), FC (Program Blocks), FB (Function Blocks), DB (Data Blocks) Số các module gọi lồng nhau: CPU 314: là 8, nếu quá thì STOP Ch4 ProgControllers 40 20
  21. 5.3.3.5. SPECIAL BLOCKS:  OB10: Time of day Interrupt - single, multiple @ fix time from SFC28 (sys function block),  OB20: Time delay Interrupt, SFC32,  OB35: Cyclic Interrupt: default 100ms,  OB40: Hardware Interrupt, báo ngắt thông qua một số module đặc biệt: SM, CP, FM, onboard IO.  OB80: Cycle time Over, default of cycle scan time 150ms,  OB81: Power Supply Fault,  OB82: Diagnostic Interrupt: from IO Module  OB85: Not Load Fault - No interrupt service block  OB87: Communication Fault - parity, time out error  OB100: Start Up Information - from STOP to START  Ch4 ProgControllers 41 5.4 Programming Languages  3 types of Prog Language STL - Statement List, LAD - Ladder and FBD - Function Block Diagram. Trong đó LAD và FBD đơn giản hơn, vậy không chuyển được qua STL, nhưng ngược lại thì được. Ch4 ProgControllers 42 21
  22. 5.4.1. Cấu trúc lệnh STL: Label: OpcodeOperand [// Comment] Data Operand: bit (logic), binary, hex, INT, DINT, REAL, S5T, TOD, DATE, C(ounter down), P - địa chỉ ô nhớ, CHAR Toán hạng là địa chỉ:  M (bit-mem), MB (byte-mem), MW (word-mem), MD (DW-mem),  I (bit-Inp), IB (byte-Inp), IW (word-Inp), ID (DW-Inp),  Q, QB, QW, QD,  T(imer), C(ounter),  PIB (analog inp - byte), PIW, PID,  PQB, PQW, PQD,  DBX (bit), DBB, DBW, DBD, Ch4 ProgControllers 43 Addresses and Data Types Permitted in the Symbol Table Only one set of mnemonics can be used throughout a symbol table. Switching between SIMATIC (German) and IEC (English) mnemonics must be done in the SIMATIC Manager using the menu command Options > Customize in the "Language" tab. IEC SIMATIC Description Data Type Value Range Ch4 ProgControllers 44 22
  23. Ch4 ProgControllers 45 Ch4 ProgControllers 46 23
  24. Ví dụ:  I 1.3 // bit 3, byte 1 from Input port PII  M 101.5 // Bit 5, byte thứ 101 trong miền M  Q 4.5 // bit 5, byte 4 của PIQ  DIB 15 // Ô nhớ 1 byte, byte thứ 15 trong DB  DBW 18 // ô nhớ 1 word, byte 18 và 19 @ DB  DB2.DBW 15// byte 15 và 16 trong khối số liệu DB2  MD 105 // 4 byte 105 108 trong DB Ch4 ProgControllers 47 Status Word: 9 bit (2 byte)  Bit 0 - FC - First Check: khi = 1 báo thực hiện 1 dãy các lệnh logic, thực hiện xong FC = 0  RLO Result of Logic Operation - kết quả của phép thực hiện logic. Ví dụ: A I 0.3 Nếu trước đó, FC=0 thì chuyển bit I 0.3 vào RLO  Nếu FC=1 thì (I 0.3 AND RLO) => RLO  STA - Status bit, tương ứng với mức logic của port. Ví dụ A I 0.3 // hoặc AN I 0.3 // đều gán cho STA logic của port I 0.  OR - giá trị logic của phép  để các phép  sau đó.  OS - Store Overflow bit - lưu lại cờ tràn ra mem cùng kết quả xử lý  OV - Overflow: báo phép tính số học tràn  CCO & CC I - condition code: cho 5 trường hợp tính toán khác nhau, ví dụ như tính toán số nguyên - không tràn 0 0 kết quả = 0 0 1 kết quả 0  BR - binary result bit: kết hợp 2 loại lập trình LAD và STL Ch4 ProgControllers 48 24
  25. 5.4.2. Instruction Groups: Ch4 ProgControllers 49  Bit logic Instruction (1st):  Lệnh gán: . Cú pháp = . Ví dụ: gán giá trị từ cổng vào I 0.2 sang Q 2.1 Network 1 A I0.2 = Q2.1  Lệnh AND () : . Cú pháp: A . Ví dụ: t/hphép AND và cất kết quả Network 1 A I0.2 A I2.1 = Q4.6 Ch4 ProgControllers 50 25
  26. Lệnh AND-NOT: . Cú pháp: AN . Ví dụ: t/hphép AND-NOT và cất kết quả Network 1 A I0.2 AN I2.1 = Q4.6 Lệnh OR: . Cú pháp O . Ví dụ: t/hphép OR và cất kết quả Network 1 A I0.2 //đọc nội dung I0.2, đưa vào RLO O I2.1= Q4.6 Ch4 ProgControllers 51  Lệnh OR-NOT: . Cú pháp ON . Ví dụ: t/hphép OR-NOT và cất kết quả Network 1 A I0.2 ON I2.1 = Q4.6  Lệnh AND với 1 biểu thức: . Cú pháp A( - lệnh không toán hạng. Nếu FC=0, kết quả logic của biểuthức sẽ cất trong RLO. Nếu FC=1, sẽ AND kết quả logic biểu thức với RLO  Ví dụ: t/hphép AND và cất kết quả Network 1 A( O I0.2 O I2.1 ) // chuyển k/quả vào RLO A( ON I1.2 O I2.3 ) = Q4.6  Tương tự như AN(, O(, ON( Ch4 ProgControllers 52 26
  27. Lệnh XOR: . Cú pháp X . Ví dụ: t/hphép XOR và cất kết quả Network 1 AN I0.2 A I0.5 X I0.6 = Q4.6 Tương tự như XN, X(, XN( Lệnh SET RLO: Lệnh CLR RLO: Lệnh NOT RLO: Ch4 ProgControllers 53  Lệnh set bit mem có điều kiện: Lệnh sẽ gán 1 vào địa chỉ ô nhớ khi RLO = 1 Cú pháp S  Lệnh clear bit mem có điều kiện: Lệnh sẽ gán 1 vào địa chỉ ô nhớ khi RLO = 1 Cú pháp R  Lệnh nhận sườn lên : theo chu kỳ các vòng quét. Nếu trước đó, RLO =0, lưu vào M10.0 - bít nhớ cờ), chu kỳ sau RLO = 1 . Cú pháp: FP . Ví dụ: A I1.0 FP M10.0 = Q4.5  Lệnh nhận sườn xuống . FN . Copy RLO sang BR - binary result Ch4 ProgControllers 54 27
  28. Comparison Instructions (2nd Group)  Description: ACCU1 and ACCU2 are compared according to the type of comparison you choose: . == ACCU1 is equal to ACCU2 . ACCU1 is greater than ACCU2 . = ACCU1 is greater than or equal to ACCU2 . <= ACCU1 is less than or equal to ACCU2  If the comparison is true, the RLO of the function is "1". The status word bits CC 1 and CC 0 indicate the relations ‘’less,” ‘’equal,” or ‘’greater.”  There are comparison instructions to perform the following functions:  ? I Compare Integer (16-bit)  ? D Compare Double Integer (32-bit)  ? R Compare Floating-point Number (32-bit) Ch4 ProgControllers 55 Conversion Instructions (3rd)  Description You can use the following instructions to convert binary coded decimal numbers and integers to other types of numbers: • BTI BCD to Integer (16-bit) • ITB Integer (16-bit) to BCD • BTD BCD to Integer (32-bit) • ITD Integer (16-bit) to Double Integer (32-bit) • DTB Double Integer (32-bit) to BCD • DTR Double Integer (32-bit) to Floating-point (32-bit IEEE-FP)  You can use one of the following instructions to form the complement of an integer or to invert the sign of a floating-point number: • INVI Ones Complement Integer (16-bit) • INVD Ones Complement Double Integer (32-bit) • NEGI Twos Complement Integer (16-bit) • NEGD Twos Complement Double Integer (32-bit) • NEGR Negate Floating-point Number (32-bit, IEEE- FP) Ch4 ProgControllers 56 28
  29.  You can use the following Change Bit Sequence in Accumulator 1 instructions to reverse the order of bytes in the low word of accumulator 1 or in the entire accumulator: • CAW Change Byte Sequence in ACCU 1-L (16-bit) • CAD Change Byte Sequence in ACCU 1 (32-bit)  You can use any of the following instructions to convert a 32-bit IEEE floating-point number in accumulator 1 to a 32-bit integer (double integer). The individual instructions differ in their method of rounding: • RND Round • TRUNC Truncate • RND+ Round to Upper Double Integer • RND- Round to Lower Double Integer Ch4 ProgControllers 57  Counter Instructions (4th)  Description: A counter is a function element of the STEP 7 programming language that acounts. Counters have an area reserved for them in the memory of your CPU. This memory area reserves one 16-bit word for each counter. The statement list instruction set supports 256 counters. To find out how many counters are available in your CPU, please refer to the CPU technical data.  Counter instructions are the only functions with access to the memory area.  You can vary the count value within this range by using the following Counter instructions: • FR Enable Counter (Free) • L Load Current Counter Value into ACCU 1 • LC Load Current Counter Value into ACCU 1, BCD • R Reset Counter • S Set Counter Preset Value • CU Counter Up • CD Counter Down Ch4 ProgControllers 58 29
  30.  Data Block Instructions (5th)  Description: You can use the Open a Data Block (OPN) instruction to open a data block as a shared data block or as an instance data block. The program itself can accomodate one open shared data block and one open instance data block at the same time.  The following Data Block instructions are available: • OPN Open a Data Block • CDB Exchange Shared DB and Instance DB • L DBLG Load Length of Shared DB in ACCU 1 • L DBNO Load Number of Shared DB in ACCU 1 • L DILG Load Length of Instance DB in ACCU1 • L DINO Load Number of Instance DB in ACCU1 Ch4 ProgControllers 59 Logic Control Instructions (6th)  Description: You can use the Jump instructions to control the flow of logic, enabling your program to interrupt its linear flow to resume scanning at a different point. You can use the LOOP instruction to call a program segment multiple times. The address of a Jump or Loop instruction is a label. A jump label may be as many as four characters, and the first character must be a letter. Jumps labels are followed with a mandatory colon ":" and must precede the program statement in a line.  Note: Please note for S7-300 CPU programs that the jump destination always (not for 318-2) forms the beginning of a Boolean logic string in the case of jump instructions. The jump destination must not be included Ch4 ProgControllersin the logic string. 60 30
  31.  You can use the following jump instructions to interrupt the normal flow of your program unconditionally: • JU Jump Unconditional • JL Jump to Labels  The following jump instructions interrupt the flow of logic in your program based on the result of logic operation (RLO) produced by the previous instruction statement: • JC Jump if RLO = 1 • JCN Jump if RLO = 0 • JCB Jump if RLO = 1 with BR • JNB Jump if RLO = 0 with BR Ch4 ProgControllers 61  Logic Control Instructions: The following jump instructions interrupt the flow of logic in your program based on the signal state of a bit in the status word: • JBI Jump if BR = 1 • JNBI Jump if BR = 0 • JO Jump if OV = 1 • JOS Jump if OS = 1  The following jump instructions interrupt the flow of logic in your program based on the result of a calculation: • JZ Jump if Zero • JN Jump if Not Zero • JP Jump if Plus • JM Jump if Minus • JPZ Jump if Plus or Zero • JMZ Jump if Minus or Zero • JUO Jump if Unordered Ch4 ProgControllers 62 31
  32.  Integer Math Instructions (7th)  Description: The math operations combine the contents of accumulators 1 and 2. The result is stored in accumulator 1. The old contents of accumulator 1 is shifted to accumulator 2. The contents of accumulator 2 remains unchanged.  In the case of CPUs with four accumulators, the contents of accumulator 3 is hen copied into accumulator 2 and the contents of accumulator 4 into accumulator 3.  The old contents of accumulator 4 remains unchanged.  Using integer math, you can carry out the following operations with two integer numbers (16 and 32 bits): • +I Add ACCU 1 and ACCU 2 as Integer (16-bit) • -I Subtract ACCU 1 from ACCU 2 as Integer (16-bit) • *I Multiply ACCU 1 and ACCU 2 as Integer (16- bit) • /I Divide ACCU 2 by ACCU 1 as Integer (16-bit) Ch4 ProgControllers 63 • + Add Integer Constant (16, 32 Bit) • +D Add ACCU 1 and ACCU 2 as Double Integer (32-bit) • -D Subtract ACCU 1 from ACCU 2 as Double Integer (32-bit) • *D Multiply ACCU 1 and ACCU 2 as Double Integer (32-bit) • /D Divide ACCU 2 by ACCU 1 as Double Integer (32-bit) • MOD Division Remainder Double Integer (32-bit) See also Evaluating the Bits of the Status Word with Integer Math Instructions. Ch4 ProgControllers 64 32
  33.  Floating-point Math Instructions (8th)  Description: The math instructions combine the contents of accumulators 1 and 2. The result is stored in accumulator 1. The old contents of accumulator 1 is shifted to accumulator 2. The contents of accumulator 2 remains unchanged.  In the case of CPUs with four accumulators, the contents of accumulator 3 is copied into accumulator 2 and the contents of accumulator 4 into accumulator 3.  The old contents of accumulator 4 remains unchanged.  The IEEE 32-bit floating-point numbers belong to the data type called REAL.  You can use the floating-point math instructions to perform the following math  instructions using two 32-bit IEEE floating-point numbers: Ch4 ProgControllers 65 • +R Add ACCU 1 and ACCU • -R Subtract ACCU 1 from ACCU 2 • *R Multiply ACCU 1 and ACCU 2 • /R Divide ACCU 2 by ACCU 1  Using floating-point math, you can carry out the following operations with one 32-bit IEEE floating- point number: • ABS Absolute Value • SQR Generate the Square • SQRT Generate the Square Root • EXP Generate the Exponential Value • LN Generate the Natural Logarithm • SIN Generate the Sine of Angles • COS Generate the Cosine of Angles • TAN Generate the Tangent of Angles • ASIN Generate the Arc Sine • ACOS Generate the Arc Cosine • ATAN Generate the Arc Tangent  See also Evaluating the Bits of the Status Word. Ch4 ProgControllers 66 33
  34.  Load and Transfer Instructions (9th)  Description: The Load (L) and Transfer (T) instructions enable you to program an interchange of information between input or output modules and memory areas, or between memory areas. The CPU executes these instructions in each scan cycle as unconditional instructions, that is, they are not affected by the result of logic operation of a statement. The following Load and Transfer instructions are available: • L Load • L STW Load Status Word into ACCU 1 • LAR1 AR2 Load Address Register 1 from Address Register 2 • LAR1 Load Address Register 1 with Double Integer (32-bit Pointer) ` Ch4 ProgControllers 67 • LAR1 Load Address Register 1 from ACCU 1 • LAR2 Load Address Register 2 with Double Integer (32-bit Pointer) • LAR2 Load Address Register 2 from ACCU 1 • T Transfer • T STW Transfer ACCU 1 into Status Word • TAR1 AR2 Transfer Address Register 1 to Address Register 2 • TAR1 Transfer Address Register 1 to Destination (32-bit Pointer) • TAR2 Transfer Address Register 2 to Destination (32-bit Pointer) • TAR1 Transfer Address Register 1 to ACCU 1 • TAR2 Transfer Address Register 2 to ACCU 1 • CAR Exchange Address Register 1 with Address Register 2 Ch4 ProgControllers 68 34
  35. Program Control Instructions (10th)  Description: The following instructions are available for performing program control instructions: • BE Block End • BEC Block End Conditional • BEU Block End Unconditional • CALL Block Call • CC Conditional Call • UC Unconditional Call • Call FB • Call FC • Call SFB • Call SFC • Call Multiple Instance • Call Block from a Library • MCR (Master Control Relay). Important Notes on Using MCR Functions • MCR( Save RLO in MCR Stack, Begin MCR • )MCR End MCR • MCRA Activate MCR Area • MCRD Deactivate MCR Area Ch4 ProgControllers 69 Shift and Rotate Instructions (11th)  11.1 Shift Instructions . Description: You can use the Shift instructions to move the contents of the low word of accumulator 1 or the contents of the whole accumulator bit by bit to the left or the right (see also CPU Registers). Shifting by n bits to the left multiplies the contents of the accumulator by “2 n ”; shifting by n bits to the right divides the contents of the accumulator by “2 n ”. For example, if you shift the binary equivalent of the decimal value 3 to the left by 3 bits, you end up with the binary equivalent of the decimal value 24 in the accumulator. If you shift the binary equivalent of the decimal value 16 to the right by 2 bits, you end up with the binary equivalent of the decimal value 4 in the accumulator. Ch4 ProgControllers 70 35
  36. The number that follows the shift instruction or a value in the low byte of the low word of accumulator 2 indicates the number of bits by which to shift. The bit places that are vacated by the shift instruction are either filled with zeros or with the signal state of the sign bit (a 0 stands for positive and a 1 stands for negative). The bit that is shifted last is loaded into the CC 1 bit of the status word. The CC 0 and OV bits of the status word are reset to 0. You can use jump instructions to evaluate the CC 1 bit. The shift operations are unconditional, that is, their execution does not depend on any special conditions. They do not affect the result of logic operation.  The following Shift instructions are available: • SSI Shift Sign Integer (16-bit) • SSD Shift Sign Double Integer (32-bit) • SLW Shift Left Word (16-bit) • SRW Shift Right Word (16-bit) • SLD Shift Left Double Word (32-bit) • SRD Shift Right Double Word (32-bit) Ch4 ProgControllers 71  11.2 Rotate Instructions  Description: You can use the Rotate instructions to rotate the entire contents of accumulator 1 bit by bit to the left or to the right (see also CPU Registers). The Rotate instructions trigger functions that are similar to the shift functions described in Section 14.1. However, the vacated bit places are filled with the signal states of the bits that are shifted out of the accumulator. The number that follows the rotate instruction or a value in the low byte of the low word of accumulator 2 indicates the number of bits by which to rotate. Depending on the instruction, rotation takes place via the CC 1 bit of the status word. The CC 0 bit of the status word is reset to 0.  The following Rotate instructions are available: • RLD Rotate Left Double Word (32-bit) • RRD Rotate Right Double Word (32-bit) • RLDA Rotate ACCU 1 Left via CC 1 (32-bit) • RRDA Rotate ACCU 1 Right via CC 1 (32-bit) Ch4 ProgControllers 72 36
  37. Timer Instructions (12th)  Description: You can find information for setting and selecting the correct time under Location of a Timer in Memory and components of a Timer. The following timer instructions are available: . FR Enable Timer (Free) . L Load Current Timer Value into ACCU 1 as Integer . LC Load Current Timer Value into ACCU 1 as BCD . R Reset Timer . SD On-Delay Timer . SE Extended Pulse Timer . SF Off-Delay Timer . SP Pulse Timer . SS Retentive On-Delay Timer Ch4 ProgControllers 73  Word Logic Instructions (13th)  Description: Word logic instructions compare pairs of words (16 bits) and double words (32 bits) bit by bit, according to Boolean logic. Each word or double word must be in one of the two accumulators. For words, the contents of the low word of accumulator 2 is combined with the contents of the low word of accumulator 1. The result of the combination is stored in the low word of accumulator 1, overwriting the old contents. For double words, the contents of accumulator 2 is combined with the contents of accumulator 1. The result of the combination is stored in accumulator 1, overwriting the old contents.  If the result does not equal 0, bit CC 1 of the status word is set to "1". If the result does equal 0, bit CC 1 of the status word is set to "0".  The following instructions are available for performing Word Logic operations: . AW AND Word (16-bit) . OW OR Word (16-bit) . XOW Exclusive OR Word (16-bit) . AD AND Double Word (32-bit) . OD OR Double Word (32-bit) . XOD Exclusive OR Double Word (32-bit) Ch4 ProgControllers 74 37
  38.  Accumulator and Address Register Instructions (14th)  Description: The following instructions are available to you for handling the contents of one or both accumulators: . TAK Toggle ACCU 1 with ACCU 2 . PUSH CPU with Two ACCUs . PUSH CPU with Four ACCUs . POP CPU with Two ACCUs . POP CPU with Four ACCUs . ENT Enter ACCU Stack . LEAVE Leave ACCU Stack . INC Increment ACCU 1-L-L . DEC Decrement ACCU 1-L-L . +AR1 Add ACCU 1 to Address Register 1 . +AR2 Add ACCU 1 to Address Register 2 . BLD Program Display Instruction (Null) . NOP 0 Null Instruction . NOP 1 Null Instruction Ch4 ProgControllers 75 38